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The Delta STE Test System is a flexible digital test platform designed for testing VLSI devices.
Delta systems offer high throughput, with integrated multi-site testing capabilities of two, four or more devices in parallel. The enVision software that controls the Delta STE employs a graphical user interface (GUI) for all components of a test program, thus facilitating creation of independent test programs for test architecture. Other key features of enVision are reusable common test objects, comprehensive off-line simulation capability, and integrated characterization of debug capabilities. Delta STE enhanced features include:
- Algorithmic Pattern Generator (APG) and Fail Log Memory (FLM) for embedded memory testing
- ACPMU Precision Time Measurement Unit for time base testing of jitter, skew, frequency, and so forth
- Hi Performance Analog Channels (HiPac) for embedded A/D and D/A channels
- Dynamically Programmable Analog Channel (DPAC) for test pattern-controlled testing of the INL/DNL parameters of A/D converters
- High Speed Data Channel (800MB/s) and Ultra High Speed Data Channel 1GB/s for high-speed data rate test application such as p1394, Fiberchannel, Sonet, and so forth
- AWS1000 1GHZ Arbitrary Waveform Generator for 100Base/T LAN chips
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